`timescale 1 ns / 1 ns
module tb_ClockDivider;
  
  // external inputs
  reg             clock         = 1'b0;           // clock
  reg             set_clock     = 1'b0;
  wire            slow_clk;
  reg    [31:0]   slow_clk_ivl  = 31'd1_000_000;          // half clock

  ClockDivider clk_div(clock, slow_clk_ivl, set_clock, slow_clk);

  // Generate 100MHz clock
  always #5 clock = ~clock;
 
  // Define standard  interval

  initial begin
      #10  set_clock = 1'b1;
      #1   set_clock = 1'b0;
  end

endmodule
